DFT Concepts

The following are the DFT points.
1) Normally scan flops are inserted while doing Design synthesis. These scan flops are stitched while doing p&r (with magma).

2) The atpg tool(like tetramax) is used to generate test vectors for these scan flops.

3) There are basically three interfaces for scan flops for doing scan flops simulation.
a) SI (scan in)
b) SO (scan out)
c) Clock

4) What are scan chains?
A. In scan test mode, scan structure allows each sequential gates to be concentrated with other sequential gates and configured as a long shift register called scan chain.

5) There are two procedure to control and enable the scan simulation.
a) Scan Enable: In scan insertion majority of the flip flops are converted into scan flops with SI (1) , D(0) and SE(select) of the mux. The chip operates in shift mode if the SE is 1 and in capture mode it SE is 0.
b) Scan Mode: Scan mode is used to control the reset and clock logic. To bypass all the logic that is coming from the main reset to the reset of each flop or to bypass all the logic that is coming from the main clk to the clk of each flop.

6) What is Scan insertion?
A. Scan insertion is the process of replacing the normal flops with the scan flops. Scan flops has a mux before the flop to that has SI (1) , D(0) and SE(select) of the mux.

7) What are the different methods of doing DFT?
A.a) MBIST (Memory Built in self test)
b) Boundry Scan
c) JTAG
d) SOC Test Bus
e) SCAN Chain

8) What is difference between bypass and compressed mode of scan simulation?
A. Compressed mode scan simulation means if we have 1000 inputs then instead of having 1000 scan daisy chains, we add a converter by which we can generate scan daisy chains for all the 1000 inputs using 100 inputs. See the attached pic. llly at the output also we have a converter that converts 1000 outputs into 100 outputs. In this way we reduce the tester time.





9) What are the different faults that can occur in DFT?
a) Stuck at fault : These fault arise due to long wire lines running adjacent to each other. If a bridge is created between these lines then short happens this is called stuck at 1. This can be verified by sending 0. llly if a open is formed then it is called stuck at 0 and can be verified by sending 1 to thescan flop.
b) Transition faults : This fault can occur if the signal strenght is very low and this is not sampled and that can result in a functional problem.

10) What are the different types of tests that we do for DFT?
a) shift mode: In this mode we shift the SI at the scan clock and expect the SO. We can control the clock from outside.
b) Capture : In this mode we change the state of the chip and then we apply the shift pattern. In this way we verify the shift pattern in every state of the chip. We capture the SO and verify the expected pattern at the out. Capture mode operates on at freq.
c) bypass : Explained in #7
d) Compressed : Explained in #7
e) min corner : sdf timing in min corner
f) max corner : sdf timing in max corner
g) Serial : Send pattern to all the scan daisy chain through SI and observe the expected pattern at the SO.
h) Parallel : Parallely send pattern to SI of each scan flop and observe the SO of that scan flop.